Embodiments of the present invention relate to equalizer circuitry.
In some transmission links (e.g., high speed transmission links), the input data (e.g., differential input data) is degraded due to high frequency loss. Equalizer circuitry (including equalizer stages) in the receiver is used to compensate for this effect so that subsequent stages (e.g., a sense amplifier in the slicer stage) can correctly detect the signal polarity. However, since many high speed protocols can have input swings as low as 100 millivolts (mV), a small voltage offset in the equalizer stages can cause degradation in the equalized signal and posts a significant challenge for the subsequent stages to interpret the correct data. These voltage offsets intrinsic to the equalizer stages can reduce the amount of differential signal swing to the slicer stage and post a more stringent requirement on the slicer stage. In extreme cases where the voltage offset is large, the equalizer stages can even flip the input data such that the output data has a different polarity from its corresponding input data.
As process dimension shrinks, the process mismatches increase, resulting in higher voltage offsets in the equalizer stages. The process mismatches include systematic mismatches (such as layout mismatches) and local variations in the process (which are even more severe at smaller process dimensions). The mismatches resulting in voltage offsets can, for example, originate in the load resistors, the differential pair, or the current sources of the equalizer stages. More specifically, mismatches between such equalizer stage components on the right and left sides of the equalizer stage can result in voltage offsets between those two sides. These mismatches cause the output voltage of the equalizer stage to have a direct current (DC) voltage offset. In other words, the difference in the output voltages on the two sides of the equalizer stage have a DC voltage offset relative to a case without mismatch between the two sides of the equalizer stage. The equalizer circuitry has an overall DC voltage offset that is the result of the DC voltage offsets in the individual equalizer stages of the equalizer circuitry.
The voltage offset degrades the jitter performance of the receiver. This jitter performance is further degraded with increased data rates and lower input voltage swings.
Thus, as process dimensions shrink, data rates increases, and input voltage swings are lowered, the jitter performance of the receiver due to voltage offset becomes increasingly worse.
Embodiments of the equalizer circuitry of the present invention arise in this context.